NXP-SCCK GPIOs and Peripherals

This device is sold as the NXP LPC43S67-A70CM Secure Cloud Connectivity Kit, order code OM13086. In the ZentriOS documentation we refer to it as the NXP-SCCK.

See also:

Contents

The following tables show the GPIOs and pins of the NXP-SCCK.

GPIO assignment is fixed, unless otherwise noted.

The Application GPIOs and pins are reassignable in a ZentriOS app. See ZentriOS SDK.

ZentriOS GPIOs

GPIO #FunctionMCU Pin
0Factory ResetP2_2
1UART0_TXP6_4
2UART0_RXP2_1
3UART1_TXP1_13
4UART1_RXP1_14
5I2C1_SDAP2_3
6I2C1_SCLP2_4
7Reserved-
8Reserved-
9Reserved-

WLAN Pins

DescriptionMCU Pin
PowerP2_12
ResetP1_7
SDIO_CLKCLK_2
SDIO_CMDP1_6
SDIO_D0P1_9
SDIO_D1P1_10
SDIO_D2P1_11
SDIO_D3P1_12

QUAD SPI

DescriptionMCU Pin
CLKP3_3
CSP3_8
MOSIP3_7
MISOP3_6
SIO2P3_5
SIO3P3_4

Application GPIOs - Reassignable

These GPIOs may be reassigned using a ZentriOS app.

GPIO #FunctionMCU Pin
10LED_BLUEP6_9
11LED_GREENP2_7
12LED_REDP6_11
13GPIOP1_0
14GPIOP1_2
15GPIOP1_1
16GPIOP6_2
17GPIOP3_2
18GPIOP2_9
19GPIOP1_8
20GPIOP2_13
21GPIOP1_3
22GPIOP1_4
23GPIOP1_5
24LCD_CMD_GPIOP6_5
25GPIOP2_6

Dynamic GPIOs can be reassigned using the PLATFORM_GPIO_DECLARE1 macro, defined in the ZentriOS SDK file: 

/api/platforms/OM13086SCCK/platform_dynamic_gpio.h

Parameters are as follows:

#define PLATFORM_GPIO_DECLARE(_gpio_num, _group, _group_pin, _port, _port_pin, func)

Default dynamic GPIO functions are assigned in the following file in the ZentriOS SDK api directory:

/api/platforms/OM13086SCCK/platform_dynamic_gpio.c

The extract below shows the default GPIO functions and pins. This symbol is defined as WEAK in platform_dynamic_gpio.c. The weak annotation allows the application to override these default definitions at compile-time. In your application, include a modified copy of the table below, without the WEAK annotation:

const zos_platform_gpio_t const zos_platform_dynamic_gpio[PLATFORM_DYNAMIC_GPIO_COUNT] =
{
    PLATFORM_GPIO_DECLARE(10, LPC_PIN_GROUP_6, 9,  LPC_GPIO_PORT_3, 5,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(11, LPC_PIN_GROUP_2, 7,  LPC_GPIO_PORT_0, 7,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(12, LPC_PIN_GROUP_6, 11, LPC_GPIO_PORT_3, 7,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(13, LPC_PIN_GROUP_1, 0,  LPC_GPIO_PORT_0, 4,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(14, LPC_PIN_GROUP_1, 2,  LPC_GPIO_PORT_0, 9,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(15, LPC_PIN_GROUP_1, 1,  LPC_GPIO_PORT_0, 8,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(16, LPC_PIN_GROUP_6, 2,  LPC_GPIO_PORT_3, 1,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(17, LPC_PIN_GROUP_3, 2,  LPC_GPIO_PORT_5, 9,  SCU_MODE_FUNC4),
    PLATFORM_GPIO_DECLARE(18, LPC_PIN_GROUP_2, 9,  LPC_GPIO_PORT_1, 10, SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(19, LPC_PIN_GROUP_1, 8,  LPC_GPIO_PORT_1, 1,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(20, LPC_PIN_GROUP_2, 13, LPC_GPIO_PORT_1, 13, SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(21, LPC_PIN_GROUP_1, 3,  LPC_GPIO_PORT_0, 10, SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(22, LPC_PIN_GROUP_1, 4,  LPC_GPIO_PORT_0, 11, SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(23, LPC_PIN_GROUP_1, 5,  LPC_GPIO_PORT_1, 8,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(24, LPC_PIN_GROUP_6, 5,  LPC_GPIO_PORT_3, 4,  SCU_MODE_FUNC0),
    PLATFORM_GPIO_DECLARE(25, LPC_PIN_GROUP_2, 6,  LPC_GPIO_PORT_5, 6,  SCU_MODE_FUNC4),
};